module float_cmp (
	clock,
	dataa,
	datab,
	aeb,
	agb,
	ageb,
	alb,
	aleb,
	aneb);

	input	  clock;
	input	[31:0]  dataa;
	input	[31:0]  datab;
	output	reg  aeb;
	output	reg  agb;
	output	reg  ageb;
	output	reg  alb;
	output	reg  aleb;
	output	reg  aneb;


	wire  aligned_dataa_sign_w = dataa[31];
	wire  [30:0]  aligned_dataa_w = {dataa[30:0]};
	wire  exp_a_all_one_w = &dataa[30:23];
	wire  exp_a_not_zero_w = |dataa[30:23];
	wire  man_a_not_zero_w = |dataa[22:0];
	wire  man_a_not_zero_w11 = |dataa[11:0];
	wire  aligned_datab_sign_w = datab[31];
	wire  [30:0]  aligned_datab_w = {datab[30:0]};
	wire  exp_b_all_one_w = &datab[30:23];
	wire  exp_b_not_zero_w = |datab[30:23];
	wire  man_b_not_zero_w = |datab[22:0];
	wire  man_b_not_zero_w11 = |datab[11:0];
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

	wire input_dataa_zero_w;
	wire input_datab_zero_w;
	wire [1:0]  man_a_not_zero_dffe1_wi;
	wire [1:0]  man_a_not_zero_merge_w;
	wire [1:0]  man_b_not_zero_dffe1_wi;
	wire [1:0]  man_b_not_zero_merge_w;
	assign input_dataa_zero_w = (~ exp_a_not_zero_w);
	assign input_datab_zero_w = (~ exp_b_not_zero_w);
	assign man_a_not_zero_dffe1_wi = {man_a_not_zero_w, man_a_not_zero_w11};
	assign man_b_not_zero_dffe1_wi = {man_b_not_zero_w, man_b_not_zero_w11};
	assign man_a_not_zero_merge_w = |man_a_not_zero_dffe1_wi[1:0];
	assign man_b_not_zero_merge_w = |man_b_not_zero_dffe1_wi[1:0];

	reg aligned_dataa_sign_adjusted_w;
	reg aligned_datab_sign_adjusted_w;
	reg input_dataa_nan_w;
	reg input_datab_nan_w;
	reg wire_cmpr1_aeb;
	reg wire_cmpr1_agb;
	reg wire_cmpr2_aeb;
	reg wire_cmpr2_agb;
	reg wire_cmpr3_aeb;
	reg wire_cmpr3_agb;
	reg wire_cmpr4_aeb;
	reg wire_cmpr4_agb;
	reg both_inputs_zero;

always @ (posedge clock)begin
	aligned_dataa_sign_adjusted_w <= (aligned_dataa_sign_w & (~ input_dataa_zero_w));
	aligned_datab_sign_adjusted_w <= (aligned_datab_sign_w & (~ input_datab_zero_w));
	input_dataa_nan_w <= (exp_a_all_one_w & man_a_not_zero_merge_w[1]);
	input_datab_nan_w <= (exp_b_all_one_w & man_b_not_zero_merge_w[1]);
	wire_cmpr1_aeb <= aligned_dataa_w[30:23] == aligned_datab_w[30:23];
	wire_cmpr1_agb <= aligned_dataa_w[30:23]  > aligned_datab_w[30:23];
	wire_cmpr2_aeb <= aligned_dataa_w[22:15] == aligned_datab_w[22:15];
	wire_cmpr2_agb <= aligned_dataa_w[22:15]  > aligned_datab_w[22:15];
	wire_cmpr3_aeb <= aligned_dataa_w[14: 7] == aligned_datab_w[14: 7];
	wire_cmpr3_agb <= aligned_dataa_w[14: 7]  > aligned_datab_w[14: 7];
	wire_cmpr4_aeb <= aligned_dataa_w[ 6: 0] == aligned_datab_w[ 6: 0];
	wire_cmpr4_agb <= aligned_dataa_w[ 6: 0]  > aligned_datab_w[ 6: 0];
	both_inputs_zero <= (input_dataa_zero_w & input_datab_zero_w);
end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

	wire  [3:0]  exp_aeb;
	wire  exp_aeb_w;
	wire  [3:0]  exp_agb;
	wire  exp_agb_w;
	wire  [3:0]  exp_eq_gt_grp;
	wire  flip_outputs_w;
	wire  out_unordered_w;
	wire  out_aeb_w;
	wire  out_agb_w;
	wire  out_ageb_w;
	wire  out_alb_w;
	wire  out_aleb_w;
	wire  out_aneb_w;

	assign exp_aeb = {wire_cmpr4_aeb, wire_cmpr3_aeb, wire_cmpr2_aeb, wire_cmpr1_aeb};
	assign exp_aeb_w = &exp_aeb[3:0];
	assign exp_agb = {wire_cmpr4_agb, wire_cmpr3_agb, wire_cmpr2_agb, wire_cmpr1_agb};
	assign exp_eq_gt_grp = {(exp_aeb[0] & exp_aeb[1] & exp_aeb[2] & exp_agb[3]), (exp_aeb[0] & exp_aeb[1] & exp_agb[2]), (exp_aeb[0] & exp_agb[1]), exp_agb[0]};
	assign exp_agb_w = |exp_eq_gt_grp[3:0];
	assign flip_outputs_w = (aligned_dataa_sign_adjusted_w & aligned_datab_sign_adjusted_w);
	assign out_unordered_w = (input_dataa_nan_w | input_datab_nan_w);

	assign out_aeb_w = ((((~ (aligned_dataa_sign_adjusted_w ^ aligned_datab_sign_adjusted_w)) & exp_aeb_w) | both_inputs_zero) & (~ out_unordered_w));
	assign out_agb_w = (
    (
      ((~ aligned_dataa_sign_adjusted_w) & aligned_datab_sign_adjusted_w)
      | ((~ aligned_dataa_sign_adjusted_w) & exp_agb_w & (~ both_inputs_zero))
      | (flip_outputs_w & (~ exp_agb_w) & (~ out_aeb_w))
    )
    & (~ out_unordered_w)
  );
	assign out_ageb_w = ((out_agb_w | out_aeb_w) & (~ out_unordered_w));
	assign out_alb_w = (((~ out_agb_w) & (~ out_aeb_w)) & (~ out_unordered_w));
	assign out_aleb_w = ((out_alb_w | out_aeb_w) & (~ out_unordered_w));
	assign out_aneb_w = ((~ out_aeb_w) & (~ out_unordered_w));


	always @ (posedge clock)begin
		aeb  <= out_aeb_w;
		agb  <= out_agb_w;
		ageb <= out_ageb_w;
		alb  <= out_alb_w;
		aleb <= out_aleb_w;
		aneb <= out_aneb_w;
  end

endmodule
